What engineering notes should I keep in mind when using Op-amp voltage-controlled resistor (VCR) designer?

A voltage-controlled resistor (VCR) is built from a JFET or a MOSFET in its ohmic region: the gate-source voltage V_GS changes the channel resistance R_DS. JFET: R_DS = V_P²/[2·I_DSS·(V_GS−V_P)], with V_P < 0 and V_GS in (V_P, 0]; MOSFET: R_DS = 1/[k·(V_GS−V_TH)], where k = µn·Cox·W/L. 运放的作用是「虚地 + 负反馈」：把 R_DS 接在inverting放大器的反馈bits置，inverting端被强制为 ≈0V。FET 的 D 端接输出、S 端接虚地，因此 V_DS = Vout；输出摆幅越大，FET 越容易偏离可变电阻区，必须用线性化网络把Resistance从信号电平中解耦。让调整管始终工作在线性区：条件是 |V_DS| < V_GS − V_P（JFE…

Op-amp voltage-controlled resistor (VCR) designer

Q: What is Op-amp voltage-controlled resistor (VCR) designer for?

Single-op-amp voltage-controlled resistor (VCR) designer: a JFET (or a MOSFET in its ohmic region) acts as the variable resistor R_DS in the feedback path of an inverting amplifier, with an AN105 linearization network (equal R_L1/R_L2 across D-G and S-G) that decouples R_DS from the signal level and keeps the pass device in its ohmic region. Compute the equivalent resistance and voltage-controlled gain from the control voltage, or Vc from a target resistance, with linear-swing, sensitivity and bandwidth checks.

Q: What is the formula for Op-amp voltage-controlled resistor (VCR) designer?

Core formula: JFET: R_DS = V_P² / [2·I_DSS·(V_GS − V_P)] ｜ MOSFET: R_DS = 1 / [k·(V_GS − V_TH)] ｜ V_GS = Vc − V_S ≈ Vc (virtual-ground source) ｜ A = −R_DS / Rg ｜ |V_DS| < V_GS − V_th (R_L1 = R_L2 linearization). The tool returns results instantly using this formula and the selected parameters.

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Single-op-amp voltage-controlled resistor (VCR) designer: a JFET (or a MOSFET in its ohmic region) acts as the variable resistor R_DS in the feedback path of an inverting amplifier, with an AN105 linearization network (equal R_L1/R_L2 across D-G and S-G) that decouples R_DS from the signal level and keeps the pass device in its ohmic region. Compute the equivalent resistance and voltage-controlled gain from the control voltage, or Vc from a target resistance, with linear-swing, sensitivity and bandwidth checks.

Key points

An op-amp voltage-controlled resistor (VCR) replaces a fixed resistor with the variable channel resistance R_DS of a FET, set by the gate-source voltage V_GS: in its ohmic region a JFET gives R_DS = V_P²/[2·I_DSS·(V_GS−V_P)] (V_P negative, V_GS in (V_P, 0]), and a MOSFET gives R_DS = 1/[k·(V_GS−V_TH)] (k = µn·Cox·W/L, V_GS > V_TH). Wired into the feedback path of an inverting op-amp amplifier, the inverting input is a virtual ground (≈0 V), so the FET sees only the output swing V_DS and stays linear, with voltage-controlled gain A = −R_DS/Rg. Linearity requires |V_DS| < V_GS−V_P (or V_GS−V_TH); a larger signal drives the FET into saturation and causes distortion. This tool computes the equivalent resistance and voltage-controlled gain range from the control voltage, or the required V_GS from a target resistance, and checks the linear swing, control sensitivity and bandwidth.

Inputs

JFET: R_DS = V_P² / [2·I_DSS·(V_GS − V_P)] ｜ MOSFET: R_DS = 1 / [k·(V_GS − V_TH)] ｜ V_GS = Vc − V_S ≈ Vc (virtual-ground source) ｜ A = −R_DS / Rg ｜ |V_DS| < V_GS − V_th (R_L1 = R_L2 linearization)

Device typeDirectionSaturation current I_DSSmAJFET datasheet parameter: saturation drain current at V_GS = 0 V and large V_DS, typically 1–20 mAPinch-off voltage V_PVJFET pinch-off voltage, a negative value (e.g. −3 V); a larger |V_P| gives a wider control range and a larger R_DS(on)Control-voltage low limit Vc(min)VLower limit of the external ground-referenced control voltage Vc; for a JFET use a negative value (closer to V_P gives a larger resistance), for a MOSFET it must exceed V_TH (e.g. 3 V)Control-voltage high limit Vc(max)VUpper limit of the external ground-referenced control voltage Vc; for a JFET the maximum is 0 V (forward bias turns the gate on), for a MOSFET 5–10 V is usableInput resistor RgkΩInput resistor of the inverting amplifier (= input impedance): the voltage-controlled gain is A = −R_DS/Rg, and it must satisfy Rg ≥ Vin·R_DS/(V_GS−V_th), otherwise the pass FET leaves its linear regionInput signal amplitude (peak)VUsed to check whether the AC swing across the FET leaves the linear region (R_DS varies with the signal → distortion)FET parallel parasitic capacitancepFFET output capacitance Coss plus wiring capacitance; with R_DS∥Rg it forms the bandwidth poleOp-amp gain-bandwidth product GBWMHzClosed-loop bandwidth is also limited by GBW / noise gain (1+|A|)Linearization resistor R_LkΩR_L1 (D→G) and R_L2 (S→G) are equal and couple V_DS/2 to the gate to cancel channel modulation (AN105 linearization), keeping R_DS independent of the signal so the FET stays in its ohmic region; recommended ≥ 10·R_DS(max)Control injection resistor R_ckΩVc is injected into the gate through R_c, isolating the external control source and preventing it from bypassing the gate bootstrap; recommended ≥ 10·R_L

Calculation model (updates with parameters)

Equivalent resistance R_DS range	150 Ω ~ 450 Ω	V_GS = 0.00 V（低阻）~ -2.00 V（高阻）
Inverting voltage-controlled gain \|A\| range	0.150 ~ 0.450V/V	A = −R_DS/Rg，Rg = 1 kΩ; the gain varies with R_DS
Gain range (dB)	-16.5 ~ -6.9 dB	20·log10(R_DS/Rg)
Low-resistance end Vc = 0.00 V	R = 150 Ω ｜ \|A\| = 0.150	Control sensitivity 33.3 %/V
High-resistance end Vc = -2.00 V	R = 450 Ω ｜ \|A\| = 0.450	Control sensitivity 100 %/V
Minimum on-resistance R_DS(on)	150 Ω	V_GS = 0V 时的Resistance：\|V_P\| / (2·I_DSS) = 150 Ω
Control sensitivity (range)	33.3 ~ 100%/V	The higher the resistance, the more sensitive: relative resistance change per 1 V of control voltage
FET linear swing limit \|V_DS\| (high-resistance end)	1.000 V	V_GS − V_P; beyond it the FET enters saturation and distortion appears
AC swing across the FET (peak, high-resistance end)	0.045 V	Input 100 mV × \|A\|; R_L couples V_DS/2 to the gate to cancel channel modulation
Input resistor Rg condition (linear region, high-resistance end)	Rg ≥ 45 Ω	Worst case (high-resistance end): Vin·R_DS(max)/(V_GS−V_th); below this value the high-resistance end saturates
Recommended minimum input resistor Rg (low distortion)	≥ 150 Ω	Keeps V_DS within 30% of the swing limit; Rg is the input impedance and should also be ≥ 10× the source impedance
Linearization resistor R_L (D-G / S-G)	100 kΩ	Both resistors equal; recommended ≥ 10·R_DS(max) = 4.5 kΩ, decoupling R_DS from the signal
Gate bootstrap swing (high-resistance end)	0.023 V	R_L1 = R_L2 makes V_GS track V_DS in the same direction, cancelling depletion-layer modulation (AN105 linearization)
Control injection resistor R_c	1 MΩ	recommended ≥ 10·R_L = 1 MΩ; isolates the external Vc so the bootstrap is not bypassed
-3 dB bandwidth (low / high-resistance end)	869.6 kHz / 689.7 kHz	寄生电容极点 61.01 MHz ｜ GBW limit 869.6 kHz
Device type	JFET	Junction FET (low noise, requires a negative gate voltage)

⚠ The R_DS of a JFET has a positive temperature coefficient of about +0.5–0.8 %/°C, and a MOSFET about +0.5–1 %/°C: over a wide temperature range use closed-loop leveling or temperature-compensate the control voltage.

Engineering notes

A voltage-controlled resistor (VCR) is built from a JFET or a MOSFET in its ohmic region: the gate-source voltage V_GS changes the channel resistance R_DS. JFET: R_DS = V_P²/[2·I_DSS·(V_GS−V_P)], with V_P < 0 and V_GS in (V_P, 0]; MOSFET: R_DS = 1/[k·(V_GS−V_TH)], where k = µn·Cox·W/L.
运放的作用是「虚地 + 负反馈」：把 R_DS 接在inverting放大器的反馈bits置，inverting端被强制为 ≈0V。FET 的 D 端接输出、S 端接虚地，因此 V_DS = Vout；输出摆幅越大，FET 越容易偏离可变电阻区，必须用线性化网络把Resistance从信号电平中解耦。
让调整管始终工作在线性区：条件是 |V_DS| < V_GS − V_P（JFET）/ V_GS − V_TH（MOSFET）。本电路加 AN105 线性化网络——R_L1（D→G）and R_L2（S→G）取等Value，couples V_DS/2 to the gate：V_DS 上升时栅压同向变化，抵消沟道耗尽layers调制，使 R_DS 只由 Vc 决定而and信号幅度无关，从而在同一 V_DS upper limit内把失真压到最低。R_L ≥ 10·R_DS(max) 以免加载信号；Vc 经 R_c（≥ 10·R_L）注入栅极，避免外部低阻控制源旁路 bootstrap。
The voltage-controlled gain is A = −R_DS/Rg: R_DS varies continuously with V_GS, so this circuit is the basis of small-signal voltage-controlled amplifiers (VCA) and AGC; Rg shifts the gain range and V_GS adjusts continuously within it.
Linear swing: the FET stays in its ohmic region while |V_DS| < V_GS − V_P (JFET) / V_GS − V_TH (MOSFET). The larger the signal the stronger the nonlinearity, so for low distortion keep the AC swing across the FET below 30% of the limit, or add linearization resistors / use matched FETs.
Control sensitivity dR/R = −dV_GS/(V_GS − V_th): near pinch-off or threshold the resistance is extremely sensitive to V_GS (hundreds of %/V), amplifying control noise, supply ripple and drift; for wide dynamic range keep the operating point where the sensitivity is moderate, or use closed-loop AGC.
Temperature drift: the R_DS of a JFET has a positive temperature coefficient of about +0.5–0.8 %/°C and a MOSFET about +0.5–1 %/°C; precision designs need temperature control, closed-loop leveling or temperature compensation of the control voltage.
Bandwidth is limited by two factors: the pole formed by R_DS∥Rg with the FET parasitic capacitance (Coss, wiring) and the op-amp GBW / noise gain (1+|A|); high-resistance settings, large capacitance and low GBW all narrow the bandwidth.
Control-voltage reference: the FET actually responds to the gate-source relative voltage V_GS = V_G − V_S, whereas an external control (DAC, divider, manual) is usually an absolute voltage to ground Vc. Here R_DS sits on the virtual ground of the inverting input, so the source S is at V_S ≈ 0 V and the ground-referenced Vc can drive the gate directly: V_GS = Vc − V_S ≈ Vc. If the same FET is used as a series/shunt VCR whose source is not grounded, the control voltage must follow the source (add a level shifter or use a floating control supply), otherwise V_GS varies with the signal and the resistance is uncontrolled.

FAQ

What is Op-amp voltage-controlled resistor (VCR) designer for?: Single-op-amp voltage-controlled resistor (VCR) designer: a JFET (or a MOSFET in its ohmic region) acts as the variable resistor R_DS in the feedback path of an inverting amplifier, with an AN105 linearization network (equal R_L1/R_L2 across D-G and S-G) that decouples R_DS from the signal level and keeps the pass device in its ohmic region. Compute the equivalent resistance and voltage-controlled gain from the control voltage, or Vc from a target resistance, with linear-swing, sensitivity and bandwidth checks.
What is the formula for Op-amp voltage-controlled resistor (VCR) designer?: Core formula: JFET: R_DS = V_P² / [2·I_DSS·(V_GS − V_P)] ｜ MOSFET: R_DS = 1 / [k·(V_GS − V_TH)] ｜ V_GS = Vc − V_S ≈ Vc (virtual-ground source) ｜ A = −R_DS / Rg ｜ |V_DS| < V_GS − V_th (R_L1 = R_L2 linearization). The tool returns results instantly using this formula and the selected parameters.
What engineering notes should I keep in mind when using Op-amp voltage-controlled resistor (VCR) designer?: A voltage-controlled resistor (VCR) is built from a JFET or a MOSFET in its ohmic region: the gate-source voltage V_GS changes the channel resistance R_DS. JFET: R_DS = V_P²/[2·I_DSS·(V_GS−V_P)], with V_P < 0 and V_GS in (V_P, 0]; MOSFET: R_DS = 1/[k·(V_GS−V_TH)], where k = µn·Cox·W/L. 运放的作用是「虚地 + 负反馈」：把 R_DS 接在inverting放大器的反馈bits置，inverting端被强制为 ≈0V。FET 的 D 端接输出、S 端接虚地，因此 V_DS = Vout；输出摆幅越大，FET 越容易偏离可变电阻区，必须用线性化网络把Resistance从信号电平中解耦。让调整管始终工作在线性区：条件是 |V_DS| < V_GS − V_P（JFE…