Crystal Load Capacitor
Crystal load-cap design: solve C1 / C2 from the specified CL and PCB / pin stray capacitance, or back-calculate actual CL and frequency pulling.
Key points
Crystal Load Capacitor: Crystal load-cap design: solve C1 / C2 from the specified CL and PCB / pin stray capacitance, or back-calculate actual CL and frequency pulling. Formula: CL = C1·C2/(C1+C2) + Cstray | symmetrical C1 = C2 = 2(CL − Cstray) | Δf/f ≈ −Cm·ΔCL/(2(C0+CL)²). Enter parameters on the DD-CAT IDE online tool page to get results instantly, with a calculation-model diagram that updates with the inputs. The datasheet CL is the load-resonance condition; external C1, C2, and stray capacitance together set actual CL — it is not simply C1 + C2. Symmetrical design: C1 = C2 = 2(CL − Cstray). Cstray includes PCB traces, pads, MCU pins, and crystal package capacitance; estimate or measure it.
Inputs
CL = C1·C2/(C1+C2) + Cstray | symmetrical C1 = C2 = 2(CL − Cstray) | Δf/f ≈ −Cm·ΔCL/(2(C0+CL)²)Calculation model (updates with parameters)
| Matching capacitors C1 / C2 | 15 pF / 15 pF | 按常用 pF 档nearest value，建议 C1 = C2 |
| Actual load capacitance CL | 12.50 pF | target 12.00 pF，偏差 0.50 pF |
| CL relative deviation | 4.17 % | CrystalloadCapacitance精度通常 ±0.5~1pF 即可 |
| Frequency pulling sensitivity | 32.7 ppm/pF | 由 C0、Cm and CL 估算 |
| Estimated frequency deviation | -16.3 ppm | CL 偏大 → Frequency偏低 |
| Crystal shunt capacitance C0 | 5.00 pF | 规格书 shunt capacitance |
| Crystal motional capacitance Cm | 20.0 fF | 规格书 motional capacitance |
| Required ideal matching caps (symmetrical) | 14.00 pF | C1 = C2 = 2(CL − Cstray) |
Engineering notes
- The datasheet CL is the load-resonance condition; external C1, C2, and stray capacitance together set actual CL — it is not simply C1 + C2.
- Symmetrical design: C1 = C2 = 2(CL − Cstray). Cstray includes PCB traces, pads, MCU pins, and crystal package capacitance; estimate or measure it.
- Too much CL lowers frequency; too little raises it. For USB / Ethernet / RF, choose a low-CL crystal and control routing and stray capacitance.
FAQ
- What is Crystal Load Capacitor for?
- Crystal load-cap design: solve C1 / C2 from the specified CL and PCB / pin stray capacitance, or back-calculate actual CL and frequency pulling.
- What is the formula for Crystal Load Capacitor?
- Core formula: CL = C1·C2/(C1+C2) + Cstray | symmetrical C1 = C2 = 2(CL − Cstray) | Δf/f ≈ −Cm·ΔCL/(2(C0+CL)²). The tool returns results instantly using this formula and the selected parameters.
- What engineering notes should I keep in mind when using Crystal Load Capacitor?
- The datasheet CL is the load-resonance condition; external C1, C2, and stray capacitance together set actual CL — it is not simply C1 + C2. Symmetrical design: C1 = C2 = 2(CL − Cstray). Cstray includes PCB traces, pads, MCU pins, and crystal package capacitance; estimate or measure it. Too much CL lowers frequency; too little raises it. For USB / Ethernet / RF, choose a low-CL crystal and control routing and stray capacitance.