CAN / CAN FD Bit Timing Calculator
Work out BRP, tq per bit, sample point and segment split from the CAN clock and target bitrate, plus the real bitrate error — before you touch the BTR registers.
Key points
CAN / CAN FD Bit Timing Calculator: Work out BRP, tq per bit, sample point and segment split from the CAN clock and target bitrate, plus the real bitrate error — before you touch the BTR registers. Formula: Bitrate = f_clk / [BRP × (1 + tseg1 + tseg2)]. Enter parameters on the DD-CAT IDE online tool page to get results instantly, with a calculation-model diagram that updates with the inputs. More tq per bit improves resynchronisation but demands a tighter oscillator; 25 tq is the CiA recommended ceiling. PROP_SEG should be at least 2× (transceiver loop delay + one-way cable delay), otherwise long buses at high bitrates produce bit errors.
Inputs
Bitrate = f_clk / [BRP × (1 + tseg1 + tseg2)]Calculation model (updates with parameters)
| Time quantum tq | 125.0 ns | |
| tq per bit (NBT) | 16 tq | CiA suggests 8–25 tq; more tq means more resynchronisation margin |
| Prescaler BRP | 1 | |
| Actual bitrate | 500 kbit/s | |
| Bitrate error | +0.000 % | CAN allows < 0.5% total oscillator + prescaler error |
| Sample point | 14/16 = 87.5 % | |
| Segment split (sync + prop + phase1 / phase2) | 1 + 7 + 7 / 2 tq | Prop segment must cover 2× the one-way transceiver + cable delay |
| SJW (sync jump width) | 2 tq |
Engineering notes
- More tq per bit improves resynchronisation but demands a tighter oscillator; 25 tq is the CiA recommended ceiling.
- PROP_SEG should be at least 2× (transceiver loop delay + one-way cable delay), otherwise long buses at high bitrates produce bit errors.
- Above 85% sample point, enable transmitter delay compensation (TDC) or the CAN FD data phase fails on transceiver delay shift.
FAQ
- What is CAN / CAN FD Bit Timing Calculator for?
- Work out BRP, tq per bit, sample point and segment split from the CAN clock and target bitrate, plus the real bitrate error — before you touch the BTR registers.
- What is the formula for CAN / CAN FD Bit Timing Calculator?
- Core formula: Bitrate = f_clk / [BRP × (1 + tseg1 + tseg2)]. The tool returns results instantly using this formula and the selected parameters.
- What engineering notes should I keep in mind when using CAN / CAN FD Bit Timing Calculator?
- More tq per bit improves resynchronisation but demands a tighter oscillator; 25 tq is the CiA recommended ceiling. PROP_SEG should be at least 2× (transceiver loop delay + one-way cable delay), otherwise long buses at high bitrates produce bit errors. Above 85% sample point, enable transmitter delay compensation (TDC) or the CAN FD data phase fails on transceiver delay shift.