Online ADC Voltage Divider Calculator: Pick R1/R2 Directly from Full-Scale Range and Vref

When a signal higher than the ADC reference voltage needs to go into an ADC, the first instinct is always "add a voltage divider." But when it comes to actually choosing R1 and R2, Vout = Vin·R2/(R1+R2) only solves half the problem: the ADC datasheet states a maximum signal source impedance (SAR ADCs often 1~50 kΩ), and if the divider's Thevenin equivalent R1∥R2 exceeds it, the sample-and-hold capacitor won't fully charge and readings read low; resistor tolerance and reference tolerance then become real, tangible errors. Every time I had to flip through the datasheet, look up standard value tables, and hand-calculate the error—too tedious. Later I settled on one online resistor divider calculator specifically for ADC sampling. Here are my usage notes and a few real measurements.

Tool URL: https://www.dd-cat.cn/tools/voltage-divider

What to enter in ADC mode

The tool has two modes. Normal divider mode "computes Vout from given R1/R2"; ADC mode is the reverse—given the full-scale range and ADC parameters, it enumerates standard resistor values to help you pick R1/R2. In ADC mode you enter:

• Input full-scale Vin,max: the maximum voltage the sensor / signal can reach;
• ADC reference voltage Vref and resolution bits (8 / 10 / 12 / 16 / 24 / 32);
• Full-scale headroom: margin reserved for overshoot, default 5%;
• ADC recommended max source impedance: the value from the datasheet (SAR commonly 1~50 kΩ);
• Divider resistor tolerance / reference voltage tolerance / ADC error (offset+gain+INL): used for the error budget;
• Resistor series: standard tables such as E24 / E96, or "no rounding" to see theoretical continuous values.

It enumerates combinations in the standard series against the target divider ratio

$$\frac{R_2}{R_1+R_2} = \frac{V_{ref}\,(1-\text{headroom})}{V_{in,max}}$$

with the constraint that the ADC-side source impedance $R_1 \parallel R_2 \le$ the datasheet limit—accuracy first, then the largest resistance values (lowest power consumption).

A real use: 10 V range into a 3.3 V, 12-bit ADC

A 10 V full-scale sensor fed into a 3.3 V, 12-bit ADC, with a 10 kΩ datasheet source-impedance limit, ordinary ±1% resistors, ±1% reference, and ADC error taken as 4 LSB:

• Recommended R1 = 18 kΩ / R2 = 8.2 kΩ (E24);
• Full-scale output 3.13 V, only 0.17% error relative to the 3.135 V target;
• Divider ratio 31.30%, scale factor 3.1951 (Vin = Vout × 3.1951);
• Source impedance 5.63 kΩ, within the 10 kΩ limit;
• Input-referred equivalent 1 LSB ≈ 2.57 mV;
• Full-scale input code 3885, full-scale utilization 94.84%;
• Worst-case input error ±2.48% (resistors 1.37% + reference 1.00% + ADC 0.10%), RSS typical error ±1.70%.

The most informative points:

• It doesn't stop at "the divider ratio is correct"—it directly tells you whether the source impedance passes. If you switch to larger-value resistors to hit the ratio more precisely, the source impedance climbs near the limit, the SAR ADC's sampling capacitor won't fully charge at the sampling instant, and readings read low—the classic trap that paper formulas miss.
• I copied the equivalent 1 LSB value straight into firmware comments: Vin = code × 2.574 mV, saving me from re-deriving it each time.
• The error budget breaks out the three sources, so you can see at a glance that the dominant errors here are the ±1% resistors (1.37%) and ±1% reference (1.00%), not the ADC itself. To improve accuracy, upgrade the resistors to ±0.1% or E96 first rather than agonizing over the ADC.

Two more scenarios

High-voltage sampling: 100 V

Same 3.3 V / 12-bit / 10 kΩ source impedance, but the range becomes 100 V:

• Recommended R1 = 68 kΩ / R2 = 2.2 kΩ, full-scale output 3.13 V, only 0.03% error;
• Divider ratio 3.13%, scale factor 31.91;
• Input-referred equivalent 1 LSB ≈ 25.7 mV;
• But the worst-case error rises to ±3.04%—resistor ratio error 1.94%, because with a small divider ratio, $dk/k=(1-k)(t_1+t_2)$ is more sensitive to tolerance;
• Branch current 1.43 mA, total power 142.5 mW—0402 resistors are no longer usable.

With a large step-down ratio the divided voltage is very small, so the same LSB becomes large when referred to the input; accuracy requirements and resistor power dissipation both rise together, and the tool calculates all of this for you.

High precision: 16-bit + ±0.1% resistors

Switch to 16-bit, headroom tightened to 2%, resistors and reference both ±0.1%, ADC error 8 LSB:

• Recommended R1 = 28.7 kΩ / R2 = 13.7 kΩ (E96), source impedance 9.27 kΩ still within limits;
• Input-referred equivalent 1 LSB ≈ 155.8 µV, full-scale utilization 97.91%;
• Worst-case error only ±0.25%, RSS typical ±0.17%.

Once the resolution goes up, the source-impedance limit and 1 LSB both force you to recalculate—which is exactly what it does for me. Also note that headroom of 0 gives the highest resolution, but over-range clips the signal; the tool warns about this.

The values I always check in the output

• Recommended R1/R2 (E24/E96) and alternatives 1/2/3: the alternatives also give error and source impedance, making it easy to choose between "high resistance to save power" and "low impedance for less disturbance";
• Full-scale output / divider ratio / scale factor: the ratio goes straight into software calibration;
• Source impedance R1∥R2: the hard constraint on the ADC side; exceeding the limit is clearly flagged "over limit";
• Input-referred equivalent 1 LSB: the code → voltage conversion factor in firmware;
• Worst-case error and typical error (RSS): the former is a linear sum, the latter a root-mean-square combination—both are given, so reports can cite either metric.

The schematic that updates with the parameters also annotates R1, R2, Vout, R1∥R2, and the error—screenshot it and paste it into the design doc.

Normal divider mode is handy too

If you only want to know the output for given R1/R2, switch to "normal divider": 5 V through 9 kΩ / 1 kΩ, the tool rounds to the nearest E24 values 9.1 kΩ / 1 kΩ, outputs 495 mV, and notes a -0.99% deviation from the original values, along with the branch current and the power dissipation of each resistor. Choosing "no rounding" gives theoretical continuous values, handy for verifying the divider ratio first.

A few notes

• Source impedance is a hard requirement: if $R_1 \parallel R_2$ exceeds the datasheet limit, either lower the resistance, lower the sample rate, or add a small capacitor at the ADC pin—don't just look at the divider ratio.
• Don't skip full-scale headroom: 0% gives the highest resolution, but overshoot will clip; generally leave 2~5%.
• Rank error sources by resistors and reference: ordinary ±1% resistors put the ratio error at the 1% level; to improve accuracy, first switch to lower-tolerance resistors / E96 and a more stable reference.
• Check power in high-voltage cases: the divider branch current is highest at maximum input, so resistor power must be checked against that and derated with at least a 2× margin.
• Match the downstream stage: this is only the divider network itself; if there's an op-amp / RC ahead of the ADC, their input impedance and bandwidth must be included in the calculation.

That's my workflow for choosing divider resistors before ADC sampling. It computes "divider ratio → standard combinations → source impedance check → equivalent LSB → error budget" in one pass, much faster than flipping through datasheets and hand-calculating, and it makes it easier to catch issues like source impedance that formula-only analysis misses.