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Online PCB Differential Trace Impedance Calculator: Solve Width & Spacing at Once, Auto-Benchmark 90/100/120Ω

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Before routing, I used an online PCB differential impedance calculator: enter trace width, spacing, dielectric thickness, and dielectric constant to get differential impedance, single-ended impedance, odd-mode impedance, coupling coefficient, and unit delay, plus auto-benchmarked tuning suggestions for 90/100/120Ω targets. Here are my notes from a few real sessions.

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Key points

PCB differential trace impedance can be quickly estimated with an online calculator: in DD-CAT's PCB differential impedance calculator, enter stackup type, trace width W, spacing S, dielectric thickness h, dielectric constant εr, and copper thickness to get differential impedance Zdiff, single-ended impedance Z0, odd-mode impedance Zdiff/2, coupling coefficient k, and unit delay (ps/mm). It uses IPC-2141A edge-coupled approximation formulas and auto-benchmarks against 90/100/120Ω targets, reporting the percentage deviation and tuning advice — set width first, then fine-tune with spacing. For example, microstrip W=0.2mm, S=0.15mm, h=0.2mm, εr=4.2, 1oz gives Zdiff≈102.2Ω, within ±5% of the 100Ω target; stripline has lower impedance for the same geometry and needs a thicker dielectric or narrower trace. Tool URL: https://www.dd-cat.cn/tools/pcb-diff.

Recently I was routing Ethernet and USB differential pairs on a board, fiddling back and forth with trace width, spacing, and stackup thickness. I kept wanting to "calculate first, then route" instead of drawing and waiting for the fab's impedance coupons to come back before reworking. Then I found an online PCB differential trace impedance calculator: plug in trace width, spacing, dielectric thickness, and dielectric constant, and the differential impedance comes out directly, with auto-benchmarked tuning suggestions for 90/100/120Ω targets. I noted down a few real sessions for future reference.

Tool URL: https://www.dd-cat.cn/tools/pcb-diff

Few Inputs, Outputs That Go a Step Further

There are just seven inputs: stackup type (surface microstrip / inner symmetric stripline), single trace width W, spacing S (edge to edge), dielectric thickness h (to the reference plane), dielectric constant εr, copper thickness, and impedance target (100 / 90 / 120Ω or free-form).

It outputs these quantities:

  • Differential impedance Zdiff: the number you care about most, compared directly against the selected target as a percentage difference;
  • Single-ended impedance Z0: the impedance of one trace to ground for the same geometry;
  • Odd-mode impedance Zodd = Zdiff/2: the impedance of a single line in the pair under odd-mode excitation;
  • Coupling coefficient k: varies with s/h — the closer the spacing (smaller s/h), the stronger the coupling;
  • Effective dielectric constant εeff and unit delay (ps/mm): for roughly estimating trace delay and matching lengths.

The formulas follow the IPC-2141A edge-coupled approximation: Zdiff = 2·Z0·(1 − k·e^(−c·s/h)), with k=0.48 / c=0.96 for microstrip and k=0.34 / c=2.9 for stripline; for single-ended Z0, microstrip uses 87/√(εr+1.41)·ln(5.98h/(0.8w+t)) and stripline uses 60/√εr·ln(4h/(0.67π(0.8w+t))). There is also a stackup cross-section diagram that redraws with the parameters, with W, S, and h labeled — change one number and it redraws.

One Real Session: Ethernet 100Ω Differential Pair

The default parameters on open are microstrip, W = 0.25mm, S = 0.15mm, h = 0.2mm, εr = 4.2, 1oz, target 100Ω, and it calculated Zdiff ≈ 91.7Ω, about -8.3% off target.

The tool gave a direct suggestion: 8% below target — reduce trace width W first, then reduce spacing S. I dropped W from 0.25 to 0.2, leaving S and h unchanged, and Zdiff became about 102.2Ω, a +2.2% deviation — inside the usual ±5% engineering tolerance, so this combination was ready to route.

This "width first, then spacing" order is worth remembering: trace width sets the single-ended Z0 (the base of Zdiff), and spacing sets the coupling coefficient for fine-tuning. If you pull spacing around first instead, impedance moves slowly and it is easy to spread the pair too far apart. The tool's note puts it more bluntly: first set the width to approach the single-ended target (about Zdiff/2 plus another 10–15%), then fine-tune with spacing.

Three Other Scenarios I Used

USB 2.0 at 90Ω

For the USB 2.0 differential pair on the same board, switching the target to 90Ω: W = 0.3, S = 0.2, h = 0.2, 1oz, it calculated about 88.2Ω, -2% off — directly usable. USB 2.0 and HDMI both run at 90Ω; just switch the target dropdown, no formula changes needed.

Inner-Layer Stripline for Gigabit Ethernet

I did not want the Gigabit pair on the surface, so I moved it to an inner symmetric stripline: W = 0.12, S = 0.15, h = 0.5 (0.5mm to each reference plane above and below), and it calculated Zdiff ≈ 99.6Ω, -0.4% off — almost dead on. Here is a counterintuitive point: stripline has reference planes both above and below, so for the same geometry the impedance is much lower than surface microstrip; to hit 100Ω you need a noticeably thicker dielectric (larger h) or narrower traces. This becomes obvious the moment you switch the stackup type.

RS-485 / CAN at 120Ω

On a board with isolated RS-485, target 120Ω: microstrip W = 0.15, S = 0.18, h = 0.2, it calculated about 119.8Ω, -0.2% off. RS-485 and CAN transceiver datasheets often call for 120Ω; the tool has a dedicated target preset, saving me from converting it myself.

Quick Reference for Common Targets

Protocol / InterfaceCommon differential impedanceParameters I tried (surface microstrip, εr=4.2, 1oz)
Ethernet / LVDS / USB3100ΩW=0.2, S=0.15, h=0.2 → ≈102Ω
USB 2.0 / HDMI90ΩW=0.3, S=0.2, h=0.2 → ≈88Ω
RS-485 / CAN120ΩW=0.15, S=0.18, h=0.2 → ≈120Ω

The sets above are examples for a 4.2 dielectric constant; in practice, use your fab's stackup.

A Few Things to Keep in Mind

  • Routing iron rule: keep differential pairs equal length, equal spacing, and on the same layer the entire way; never cross a split plane; add return ground vias right next to layer transitions. Getting the impedance right is only the first step — lose routing discipline and the pair is still ruined.
  • Tuning order: width first, then spacing (see the Ethernet section above).
  • The formulas are engineering approximations: the IPC-2141A set is a ±5%-class estimate; when s/h drops below 0.2 you are in the strong-coupling region and the error grows. Before production on an impedance board, always have your fab simulate against your stackup and provide impedance coupons.
  • Unit delay: the ps/mm in the output is 3.333·√εeff — about 5.9ps/mm for microstrip and 6.8ps/mm for stripline. For length matching, a 1mm trace difference is about 5.9ps — that is the magnitude you are comparing.
  • Do not fudge copper thickness and εr: 1oz copper is t ≈ 35µm and 2oz ≈ 70µm; FR-4 εr is roughly 4.2–4.7, and high-frequency laminates are a different story. Get these baseline numbers wrong and the results will be off.

Conclusion

The hard part of differential impedance has never been the formulas themselves, but "which direction to adjust when a parameter moves." This tool hands you the deviation and the tuning direction together, plus a stackup cross-section diagram. My basic flow now is: run it once before routing to set initial W/S values, then go into the EDA tool to constrain equal length and equal spacing. The link is in my bookmarks, right next to the voltage divider and RC filter tools.

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